ADVANCED VLSI AND DESIGN LAB [J205]
|Sub Code: EC8381||Sub Name: ADVANCED VLSI AND DESIGN LAB|
|Year: III||Semester: VI|
LIST OF EXPERIMENTS
FPGA BASED EXPERIMENTS
- HDL based design entry and simulation of simple counters, state machines, adders (min 8 bit) and multipliers (4 bit min).
- Synthesis, P&R and post P&R simulation of the components simulated in (I) above. Critical paths and static timing analysis results to be identified. Identify and verify possible conditions under which the blocks will fail to work correctly.
- Hardware fusing and testing of each of the blocks simulated in (I). Use of either chipscope feature (Xilinx) or the signal tap feature (Altera) is a must. Invoke the PLL and demonstrate the use of the PLL module for clock generation in FPGAs.
IC DESIGN EXPERIMENTS: (BASED ON CADENCE / MENTOR GRAPHICS / EQUIVALENT)
- Design and simulation of a simple 5 transistor differential amplifier. Measure gain, ICMR, and CMRR
- Layout generation, parasitic extraction and resimulation of the circuit designed in (I)
- Synthesis and Standard cell based design of an circuits simulated in 1(I) above. Identification of critical paths, power consumption.
- For expt (c) above, P&R, power and clock routing, and post P&R simulation.
- Analysis of results of static timing analysis.
BEYOND THE SYLLABUS
- To simulate and synthesis real time clock using Verilog
- To design a CMOS inverter DC characteristics,transient characteristics and switching times
LIST OF EQUIPMENTS